Since the advent of the semiconductor, scientists and engineers have strived to reduce the power consumption of semiconductor devices, e.g., Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). Since the amount of power consumed by a MOSFET is proportional to the size of the device, the goal of reducing power demands has resulted in a goal of obtaining ever smaller MOSFETs.
Today, it is common to manufacture MOSFETs on the scale of 0.25 microns (wherein a MOSFET's size is characterized by the length of its gate). To date, these reductions in MOSFET sizes have principally resulted from improvements in the equipment and apparatus used to manufacture semiconductors. The basic process flow of manufacturing MOSFETs has remained substantially unchanged since the introduction of the poly-silicon gate which enables self-aligned flow. The current method of producing a MOSFET on a polished silicon wafer encompasses numerous individual steps which are often grouped into major process steps. These process steps commonly begin with an undoped silicon wafer 10, as shown in FIG. 1a, on which a pad oxide layer 11 and a nitride layer 13 are formed.
The process, which the present invention addresses, specifically begins with isolation, wherein the undoped silicon wafer 10 is divided by a number of isolation regions 12 (such as SiO.sub.2) into separate areas in which individual devices are to be located, as shown in FIG. 1b.
After isolation, a sacrificial oxide is often suitably deposited above the active regions; followed by the implantantation of the deep well. Well implantation determines the electrical properties of the device (i.e., whether the transistor will be NMOS or PMOS). For example, an NMOS has a p-doped well 16 (identified by the "p") and a PMOS has an n-doped well 18 (identified by the "n"), as shown in FIG. 1c.
After well implantation, the gate stack is commonly formed. A gate oxide 20 is grown in the location where the channel will eventually be formed. A poly-silicon layer 22 is then deposited on top of the gate oxide 20, as shown in FIG. 1d.
After formation of the gate stack, the gate (the combination of the gate oxide 20 and the poly-silicon 22) is patterned, as shown in FIG. 1e. This step basically determines the length of the gate 22, and designates the level of technology (i.e., in the realm of semiconductor devices, the gate length is commonly used as a benchmark of the technology, wherein a smaller gate length indicates a more advanced technology).
After forming and patterning the gate, the source and drain are implanted. Source and drain implantation commonly occurs in two steps, the first of which is commonly referred to as the implantation of Lightly Doped Drains and Source (LDDS). In this step, lightly doped regions 25 are created on either side of the gate, as shown in FIG. 1f. The device structure is then commonly subjected to Rapid Thermal Processing (RTP), which anneals defects cause by ion implantation and electrically actives the doping impurities. In the second step of source and drain implantation, spacers 26 are formed on either side of the gate and then highly doped junction regions 27 are implanted using known techniques and dopants, as shown in FIG. 1g. The junctions are then thermally annealed using known annealing processes.
After implanting the source and drain, the last step provides for the formation of ohmic contacts through self-aligned silicidation. During silicidation, the region above the source, drain, and the poly-silicon gate are covered with a low resistivity metallic silicide film 30, as shown in FIG. 1h. The spacers 26 physically and electrically separate the gate 20/22 from the source and drain junctions 25/27.
While the process described in detail above has proven to be an effective method of producing MOSFETs on the scale of 0.18 microns, utilizing this process has proven to be highly undesirable and faces tremendous technological hurdles when applied on scales of less than 0.13 microns. One of these hurdles is the short channel effect, which often occurs when the length of the gate decreases below 0.13 microns. As the gate length decreases, the depletion regions (i.e., the regions of the source and drain under the gate) merge and the gate loses control of the current.
One approach at preventing the short channel effect from occurring is to shrink the depth of the channel between the source and the drain. While shrinking the channel depth has proven feasible for devices with gate lengths as small as 0.25 microns, for devices smaller than 0.13 microns significant fabrication difficulties often arise. Some of these difficulties are due to the diffusion properties of boron and other potential p-type dopants (gallium and indium) in silicon. In the standard process flow, Rapid Thermal Processing (RTP) is commonly used to electrically activate dopants and anneal any defects which may have occurred during the various deposition stages. When RTP is utilized on a boron laced substrate, however, excessive diffusion often occurs and the channel widens, thereby giving rise to the short channel effect.
In addition to controlling the diffusion of boron in the channel, the profiles under the gate also need to be sharper with, ideally, the lowest concentration possible occurring at the silicon/gate insulator interface. FIG. 2a shows a shallow profile 32 and FIG. 2b shows the desired steep profile 34. FIG. 2c shows a relative graph (for illustrative purpose only, and not to reflect actual doping profiles) of the doping concentration versus the depth of the structure for a shallow profile (i.e., along the line A--A in FIG. 2a) and a deep profile (i.e., along the line BB in FIG. 2b). As shown in FIG. 2c, the shallow profile 32 ("A--A") has a lower doping concentration in the substrate closest to the gate oxide (i.e., the area of the graph indicated by "100") and a larger doping concentration deeper in the substrate (i.e., area "102"). In contrast, the steep profile 34 (i.e., "B--B" or area "104") has a constant doping concentration throughout the substrate. In standard, CMOS devices, the shallow profile (i.e., "A--A") is desired because it helps suppress punch through. However, in &lt;0.13 micron generation transistors, the steep profile 34 is desired because it results in better charge carrier mobility and therefore a higher current drive capability.
Under currently available methods, these steeper profiles can be obtained via two methods, Super Steep Retrograde Well (SSRW) and Super Halo. However, neither of these approaches is suitable for &lt;0.13 micron architectures. SSRW is unsuitable for &lt;0.13 micron generation transistors because in order to achieve the sharp profiles desired, SSRW requires numerous thermal cycles which diffuse dopants and often give rise to the short channel effect. Similarly, the Super Halo method requires very abrupt doping profiles under the gate and junctions of the MOSFET which can be very difficult to obtain with current process flows. Therefore, currently available processes and systems can not make profiles suitable for the &lt;0.13 micron generation.
Another problem encountered in producing devices in the &lt;0.13 micron generation using the present method arises from the lightly doped extensions of the source and drain into the channel (for example, see FIG. 1f, item 25). Originally, these lightly doped extensions were introduced to prevent the Hot Carrier Effect (HCE). HCE is the phenomenon which occurs in silicon when charge carriers in the drain are accelerated by a high energy field. The charge carriers often become hot, overcome the gate oxide barrier, and inject into the gate. HCE will ultimately degrade the performance of the device to the point of unreliability.
HCE, however, is less of a concern in devices with low operating voltages. Since the operating voltage of the device decreases as the gate length decreases, in &lt;0.13 micron devices, the electric field generated does not accelerate the charge carriers to the point of thermal break through. Additionally, as the gate voltage of the device decreases, the series resistance of the source and drain regions becomes ever more important when compared to the resistance of the inversion layer.
Since the current drive is proportional to the voltage divided by the resistance (I=V/R), it is desirable to decrease the resistance and thus maintain a high current drive in a low voltage device. Therefore, for &lt;0.13 micron generation devices it is desirable to have steep, highly doped sources and drains. As previously stated, fabricating such regions using currently available methods is extremely difficult.
Additionally, for very low voltage circuits (1 Volt and below) it is expected that silicon dioxide, the MOS gate insulator commonly used, will be replaced by another material with a larger dielectric constant. The most promising candidates to replace SiO.sub.2 are metal oxides. Unfortunately, metal oxides generally can not be simply introduced into the current process flow in place of SiO.sub.2. Chemical, mechanical, and electrical stability problems and contamination concerns make integration of metal oxides into the current process flow difficult and problematic. Since SiO.sub.2 has proven to be highly undesirable for low power devices, the inability of the current processes to efficiently utilize metal oxides may retard the introduction of low power circuits, especially those to be powered by batteries.
The factors identified above create extreme difficulties in producing semiconductor devices &lt;0.13 micron in size using the conventional process flow. Therefore, a process flow for producing semiconductor devices for the &lt;0.13 micron generation is needed.